In some microprocessors a trace cache is used to store a series of decoded instructions for execution by a processor. The decoded instructions are produced from corresponding originating instructions. Occasionally one or more of the originating instructions are modified (by memory write instructions, for example) during the time the decoded instructions are stored in the trace cache. Then the decoded instructions (now invalid) are removed from the trace cache. Conventional removal of these decoded instructions is inefficient in terms of power and performance.
Accordingly, what is needed is a more effective way of managing a microprocessor trace cache. The present invention addresses such a need.